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A major activity in the APPRASE Project at Liverpool Hope University is to migrate Fortran programs to FPGAs.
The objectives
- To migrate an entire program to the FPGA and its associated memory.
- To develop a flexible migration path targeted to a range of hardware and software environments.
- To automate the entire process.
Why Fortran?
The high level language compilers for FPGAs are C compilers. We have chosen to migrate Fortran because:
- Most super-computer and high performance computer programs are written in Fortran.
- The existing C compilers for FPGAs compile a sub-set C language. Those which support a wide range of C functionality probably do so with limited efficiency. We need to generate a sub-set of C, so we need to re-engineer the code no matter what we start with.
- We have powerful tools to re-engineer and to convert Fortran.
The Tools
Our tools are made up of three layers.
- WinFPT is an existing commercial product. It contains a powerful static semantic analyser which cross references variables and program attributes across all of the subroutines and functions in a program.
- The WinFPT API is an application programming layer added to WinFPT. It allows a user to write customised code which accesses the internal WinFPT data structures which describe the user's program.
- The Fortran to FPGA C compiler is written in C++. It calls components of the WinFPT API to access the attributes of variables for declarations and to access the token stream in the executable Fortran statements to generate the C code.
The Migration Pipeline
The migration pipeline is made up of a sequence of small separate steps. The target of the pipeline is Handel, Mitrion or Dime C, and we may ultimately generate VHDL directly. Not all of the steps are needed for every target.
Testing the Pipeline
We will not model the weather system of the South Atlantic in the first run. We will start with small, well understood Fortran programs which run on PCs. Each step in the pipeline generates a modified code which can be run on a PC, either in Fortran or in C, and tested against the original PC run. After each step we must be satisified that we understand any changes in the output and that the changes are acceptable.
The AD10 Legacy
One of the project members, John Collins, was co-author of the compiler and run-time system for the AD10 simulation computer in the early 1980's. The AD10 was the principal simulation design tool for Space Shuttle, and for many nuclear power plant and missile systems. Three aspects of the technology were very similar to FPGAs:
- It was highly parallel, with fine-grain parallelism. The compiler contained an optimising paralleliser which easily outperformed human attempts to parallelise the code (The “DAREA” optimiser).
- It was fixed point, with a built-in management system for scaling.
- It was hosted on a general purpose computer.
We hope to apply some of this technology to the FPGA pipeline.
High Performance Computing
In addition to the above objectives a high performance computing machine lovingly called ‘The BEAST’ has been installed and caters to research and development and solving demanding computing problems such as Graphics Rendering and Scientific Calculations. Presently, experimentation with net rendering performance with and without virtualization is on-going.
Technical details of ‘The BEAST’
The machine has 4 nodes of Dell PowerEdge 1950 Servers each with dual Intel Xeon Quadcore Processors and 4GB of main memory thus providing a cluster with 32 cores. The 4 nodes are connected via a 1 gigabit Ethernet connection and provide uninterrupted services over multiple operating systems. Secondary memory is available in the form of dual 73GB hard-disks per node thus providing a total storage capacity of 584GB. The 4 nodes are connected to a HP Compaq dual core machine which acts a gateway.
The nodes can be reconfigured as per users requirements and people from various communities are welcome to contact the Project Team with any ideas, suggestion or queries.
The Project Team
Brian Farrimond
Principal Lecturer –Liverpool Hope University
Honorary Research Associate – University of Cape Town
Member of SimCon Ltd.
Email:
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John Collins
Associate Lecturer – Liverpool Hope University
Honorary Research Associate – University of Cape Town
Member of SimCon Ltd.
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Ashutosh Sharma
Project Development Officer
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The team would like to thank Prof. Mike Inggs at UCT, Allan Cantle at Nallatech Ltd. and Members of the ACE SIG for their advice and support in addition to Dr. David Reid at Liverpool Hope University for his expertise on FPGA’s.
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